As electronic devices achieve a higher processing speed, a problem of electromagnetic noise propagation within a printed circuit board becomes conspicuous. Electromagnetic noise (which will be referred to simply as noise hereinbelow) is caused by switching noise in IC's or leakage from signal chains. The noise propagates throughout the printed circuit board. As a result, the noise enters input/output terminals in LSI's to deteriorate their characteristics. Moreover, it is a main factor of a problem of EMI (leaked electromagnetic waves). Therefore, it is important to take account of a behavior of noise within a multi-layer printed circuit board in designing the board. To this end, it is important to analyze electromagnetic wave noise propagation by expressing it using a linear time-invariant equivalent circuit model suitable for SPICE, which is a general-purpose circuit simulator, to create the model. Currently, we have had a reliable equivalent circuit model for a structure of a printed circuit board having stacked conductive planes of the same shape. However, no reliable model has been proposed for a structure having stacked conductive planes of different shapes or having a plurality of conductive planes in the same layer. There has been proposed a noise analysis method, which is limited to a pair of conductor planes of the same shape, disclosed in a paper (T. Harada, et al.: “Power-Distribution-Plane Analysis for Multilayer Printed Circuit Boards with SPICE,” Proceeding of 2000 IEMT/IMC symposium, pp. 420-425, April, 2000), for example. This method comprises approximating a conductor plane pair by a planar circuit and defining a fine mesh to create an equivalent circuit model, and noise propagation can be determined using a circuit solver such as SPICE from a noise source at a joint between a power supply terminal of an LSI and the printed circuit board.
Now a conventional analysis method for a conductor plane pair will be briefly described with reference to the accompanying drawings. FIG. 17 shows an LSI package and a printed circuit board connected thereto. The printed circuit board includes a pair of conductor planes representing a power-supply/ground plane pair. In FIG. 17, designations are as follows: 100: an LSI package, 101: an LSI power supply terminal, 102: an LSI ground terminal, 103: a printed circuit board power supply terminal, 104: a printed circuit board ground terminal, 105: a printed circuit board dielectric layer, 106: a printed circuit board ground plane, 107: a printed circuit board power supply plane, 108: a via connecting the printed circuit board power supply plane with power supply terminal, and 109: a clearance hole through the ground plane 106 for passing the via 108 therethrough. An actual printed circuit board is additionally mounted with a power supply terminal and a ground terminal for direct current power supply, as well as a decoupling pad and wirings for connecting the terminals together as needed and as appropriate.
FIG. 18 is a diagram showing the pair of conductor planes in FIG. 17 represented by an equivalent circuit model using a mesh. Reference numeral 201 designates a top view of the equivalent circuit model of the conductor plane pair. Reference symbols a(b) each designate the size of a transverse edge (the size of a longitudinal edge) of the conductor plane pair. Reference symbols Δx(Δy) each designate the size of a transverse edge (the size of a longitudinal edge) of a cell of the mesh. Reference numeral 202 is a specific circuit representation of one cell of the mesh of the circuit model 201 of the conductor plane pair. Reference symbols Rx(Ry) each designate a resistance along a transverse side (a resistance along a longitudinal side). Lx(Ly) each designate an inductance in the transverse direction (an inductance in the longitudinal direction). Reference numeral 203 designates a side view of the equivalent circuit model of the conductor plane pair, where H designates a thickness of the conductor plane pair. Reference numeral 204 is a specific representation of a circuit constant on one edge in a height direction of the circuit model designated by 203. Reference symbols Cz(Gz) each designate a capacitance (conductance). Reference numeral 205 designates a ground point in the circuit model.
FIG. 19 shows a model in which current from the LSI power supply terminal in FIG. 17 entering the printed circuit board is regarded as a current source and the current source is connected to the equivalent circuit model in FIG. 18. Reference numeral 301 designates a current source in the modeled LSI power supply terminal, and 302 designates a side view of the equivalent circuit model of the printed circuit board taken through a plane in which the power supply terminal lies. Reference numeral 303 designates a node corresponding to a part in which the power supply terminal of the printed circuit board lies. By solving the model in FIG. 19 using a circuit solver such as SPICE, a distribution of voltage at the nodes can be calculated. Thus, a distribution of noise in a printed circuit board can be known.
Another method of creating an equivalent circuit for a case in which a plurality of pairs of conductive planes are present and upper and lower plane pairs are electrically connected to each other through a via is disclosed in a paper (N. Kobayashi, et al.: “Analysis of Multilayered Power-Distribution Planes with Via Structures using SPICE,” IEICE Technical Report, EMCJ2005-97, pp. 25-30, October, 2005). In particular, for a multi-layer printed circuit board in which two plane pairs are present and upper and lower plane pairs are connected to each other through a via as shown in FIG. 20, and representing an upper plane pair as Pair-1 and a lower plane pair as Pair-2, each plane pair is represented by creating the aforementioned equivalent circuit model, and upper and lower nodes electrically connected through the via are connected with an equivalent circuit of a single inductance or a via model that was separately prepared, as shown in FIG. 21.
Non-patent Document 1: T. Harada, et al.: “Power-Distribution-Plane Analysis for Multilayer Printed Circuit Boards with SPICE,” Proceeding of 2000 IEMT/IMC symposium, pp. 420-425, April, 2000.
Non-Patent Document 2: N. Kobayashi, et al.: “Analysis of Multilayered Power-Distribution Planes with Via Structures using SPICE,” IEICE Technical Report, EMCJ2005-97, pp. 25-30, October, 2005.